A device shown in FIG. 5 is contrived as an encryptor/decryptor conforming with an encryption algorithm of DES (Data Encryption Standard).
Key data (secret key) and input data (plain text data or encrypted text data) are each composed of 64 bits and are latched in latch circuits 81 and 82, respectively, according to a clock CLK. And a mode signal indicative of encryption or decryption is latched in a latch circuit 83 according to the clock CLK.
The key data outputted from the latch circuit 81 are supplied to a key generator 90, and the key data K1 to K16 of 16 stages each composed of 48 bits are outputted sequentially from the key generator 90.
More specifically, the 64-bit key data outputted from the latch circuit, 81 are converted into 56-bit key data in a conversion circuit 91, and higher-order 28-bit data and lower-order 28-bit data are shifted by 1 bit or 2 bits in shift circuits 93 and 94, and then are combined together to form 56-bit key data, which are converted into 48-bit key data in a conversion circuit 95, whereby first-stage key data are generated.
Thereafter similar bit shift and conversion are executed, so that key data of 16 stages are generated and then are inputted to a selector 99. Subsequently the selector 99 is controlled by the mode signal outputted from the latch circuit 83, and key data K1 to K16 of 16 stages each composed of 48 bits are outputted sequentially according to the pulses of the clock CLK.
The output data (plain text data or encrypted text data) from the latch circuit 82 are supplied to a calculator 100, where the following calculation is executed.
First, the 64-bit data outputted from the latch circuit 82 are transposed bit by bit in an initial transposition circuit 101, and the lower-order 32 bits out of the entire 64-bit data obtained after such initial transposition and the key data K1 are calculated together in a first-stage conversion circuit 102, and further after conversion by the use of a function F, the 32-bit data outputted from the conversion circuit 102 and the higher-order 32 bits out of the entire 64-bit data after the initial transposition are calculated together in an XOR (exclusive OR) circuit 103.
Subsequently, the 32-bit data outputted from the XOR circuit 103 and the key data K2 are calculated together in a second-stage conversion circuit 104, and after conversion by the use of a function F, the 32-bit data outputted from the conversion circuit 104 and the lower-order 32 bits out of the entire 64-bit data obtained after the initial transposition are calculated together in an XOR circuit 105.
Thereafter, similarly to the above, the higher-order 32 bits and the lower-order 32 bits are mutually replaced and, after execution of the calculations in the third and subsequent stages, the 32-bit data inputted to a 16th-stage conversion circuit 107 and the 32-bit data outputted from a 16th-stage XOR circuit 108 are combined with each other, and the 64-bit data obtained after such combination are transposed bit by bit in an inverse transposition circuit 109.
The 64-bit data after such inverse transposition are latched in a latch circuit 84 according to the clock CLK, and then either encrypted or decrypted data are outputted from the latch circuit 84.
However, in the encryption/decryption calculating device described above, the key generator 90 is an asynchronous circuit including none of latch circuit (sampling circuit), wherein 16-stage key data are generated at a time from the input key data and are merely selected by the selector 99, so that much noises (changes in the signal line potential) are superposed, in the vicinities of the change points, on the key data K1 to K16 outputted from the key generator 90, and therefore the power consumption in the calculator 100 is increased.
In view of such problems, an object of the present invention resides in realizing an improved calculating device which is adapted for remarkable decrease of the power consumption.